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copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. low-, wide- voltage battery front-end dc/dc converter single-cell li-ion, ni-rich, si-anode applications features general description input voltage range: 2.3 to 5v 9 m a quiescent current in low iq bypass mode fixed output voltage options: 3.15v/3.35v/i2c programmable APW7281: voutfloor_th=3.15v (default) (i2c program- mable) voutroof_th=3.35v (default) (i2c programm- able) voltage scaling management by vsel pin - vsel=high, minimum vout=voutroof_th - vsel=low, minimum vout=voutfloor_th current limit at boost mode up to 95% efficiency auto true bypass operation when v in > target v out internal synchronous rectifier forced bypass mode by external bypb control mode control pfm/pwm; forced pwm mode short circuit protection while true bypass mode low operating quiescent current<150 m a available in wlcsp1.66x1.66-16 package the APW7281 is a boost converter with bypass mode. the operations between dc/dc boost and bypass mode are transitioned seamlessly. applications simplified application circuit sw vin vsel en bypb scl sda pgnd agnd gpio (pg) vout i2c bus interupt battery to system, v bat preset minimum level~ v bat pfm/pwm mode single-cell ni-rich, si-anode, li-ion, lifepo4 smart phones or tablet pcs 2.5v/3g/4g mini-module data cards
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 2 ordering and marking information note: anpec lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with rohs and compatible with both snpb and lead-free soldiering operations. anpec lead-free products meet or exceed the leadfree requirements of ipc/jedec j std-020c for msl classification at lead-free peak reflow temperature. pin configuration APW7281 package code ha: wlcsp1.6x1.6-16 operating ambient temperature range i: -40~85 handling code tr : tape & reel assembly material g : halogen and lead free device assembly material handling code temperature range package code APW7281 ha : w81 x x - date code en gpio vin vin vsel scl vout bypb sda sw agnd pgnd pgnd pgnd a b c d 1 2 3 4 vout sw APW7281 (top view)
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 3 absolute maximum ratings (note 1) note1:absolute maximum ratings are those values beyond which the life of a device may be impaired. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics (note 2) symbol parameter typical value unit q ja junction-to-ambient resistance in free air (note 2) 78 o c/w symbol parameter rating unit v vin vin supply voltage (vin to gnd) -0.3~5.5 v v vout vout voltage (vout to gnd) -0.3~6 v dc -0.3~5.5 v v sw sw voltage (sw to gnd) 2.3mhz, transient 2ns -0.3~6 v en, bypb, vsel, gpio, scl, sda (pin to gnd) -0.3~5.5 v continuous average current into sw 1.8 a peak current into sw 5.5 a power dissipation internal limited w t j maximum junction temperature 150 o c t stg storage temperature -65 ~ 150 o c t sdr maximum lead soldering temperature(10 seconds) 260 o c note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. the exposed pad of xxxxx is soldered directly on the pcb. symbol parameter range unit v vin vin supply voltage (vin to gnd) 2.3 ~ 4.85 v l inductor 200 ~ 800 nh c o output capacitor 9 ~ 100 m f maximum load current during start-up 250 ma t a ambient temperature -40 ~ 85 t j junction temperature -40 ~ 125 recommended operating conditions (note 3) note 3: refer to the typical application circuit.
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 4 electrical characteristics APW7281 symbol parameter test conditions min typ max unit quiescent current dc/dc boost mode, not switching, i out = 0ma, v in = 3.2v, v out = 3.4v - 47 65 m a pass-through mode(auto), v en = 1.8v, v bypb = 1.8v, v in = 3.6v - 27 42 m a i vin_q operating quiescent current into vin pass-through mode(forced), v en =1.8v, v bypb =0v, v in =3.6v - 15 25 m a operating quiescent current into vout dc/dc boost mode, not switching, i out =0ma, v in =3.2v, v out =3.4v - 8.5 19 m a operating quiescent in shutdown mode v en = v bypb = 0v, v in = 3.6v - 2.6 9 m a i vin_sd operating quiescent in shutdown mode v en = 0v, v bypb = 1.8v, v in = 3.6v - - 5 m a under voltage lockout i vin_uvlo vin under-voltage lockout threshold v in rising 2.1 2.3 2.5 v vin under-voltage lockout threshold v in falling - 0.1 - v power on delay - 400 - m s en, bypb, vsel, mode, gpio, pg, scl, sda v il low-level input voltage - - 0.4 v v ih high-level input voltage 1.2 - - v input logic high threshold 0.65 0.875 1.1 v input logic high threshold hysteresis 50 - 150 mv v ol sda, gpio low-level output voltage i ol = 8ma - - 0.3 v en, vsel, bypb internal pull-down resistance input< 0.4v - 300 - k v in =3.2v, input connected to v in - - 0.5 m a en, vsel, bypb input leakage current v in = 3.2v, input connected to agnd - 0 - m a gpio /rst start-up delay time - 7.2 - ms en, vsel, bypb, mode, pg input capacitance input connected to agnd or vin 9 pf sda, scl, gpio input capacitance input connected to agnd or vin 9 pf output boost converter output accuracy -1.5 - +1.5 % 2.65v Q v in Q v out_th -150mv, i out = 0ma, pwm operation -2 - +2 % pfm mode output ripple voltage pfm operation, i out = 1ma - 30 - mv pk v out pwm mode output ripple voltage pwm operation, i out = 500ma - 15 - mv pk unless otherwise specified, these specifications apply over v in =3.2v, v out =3.4v, v en =1.8v, v sel =1.8v, v bypb =1.8v and t a =40 ~ 85 o c. typical values are at t a =25 o c.
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 5 electrical characteristics (cont.) APW7281 symbol parameter test conditions min typ max unit power switch low-side mosfet on-resistance v in = 3.2v, v out = 3.5v, - 45 80 m high-side mosfet on-resistance v in = 3.2v, v out = 3.5v, - 40 70 m pass-through mosfet on-resistance v in = 3.2v, v out = 3.5v, - 35 60 m reverse leakage current into sw en = agnd, v in = v out = sw = 3.5v, -40 Q t j Q 85 - 0.1 2 m a reverse leakage current into vout en=bypb=vin, v in = 2.9v, v out = 4.4v, v sw = 0v, device not switching, -40 Q t j Q 85 - 0.1 2 m a vout sink capability en=agnd, v in =v bypb =3.6v, i out =-10ma - - 0.3 v protections inductor peak current limit v in = 2.9v, v out = 3.5v, auto pfm/pwm -40 Q t j Q 85 , ilim[3:0]=1011, 2.9 3.4 3.9 a en = bypb = agnd, v in = 3.2v 4 5 6 a pass-through mode ocp threshold en = vin, bypb = don t care, v in = 3.2v 5.6 7.4 9.1 a linear mode current limit (phase 1) v in - v out R 300mv - 650 - ma linear mode current limit (phase 2) ( ilim[3:0]>1000) v in - v out R 300mv - 2 - a linear mode phase 1 timeout time - 750 - m s linear mode phase 2 timeout time ( ilim[3:0]>1000) - 1.5 - ms hiccup mode delay time between start-ups - 1 - ms boost mode high-side mosfet ocp threshold low-side mosfet ocp - ilim +50% - a oscillator f osc oscillator frequency in boost mode v in = 2.7v, v out = 3.5v 2 2.3 2.6 mhz thermal shutdown thermal shutdown threshold 140 160 - o c thermal shutdown threshold hysteresis - 30 - o c timing start-up time v in = 3.2v, v out_th = 3.4v(01011), r load =50 , time from active v in to v out settled - 200 - m s /rst(gpio) rise time - - 200 ns unless otherwise specified, these specifications apply over v in =3.2v, v out =3.4v, v en =1.8v, v sel =1.8v, v bypb =1.8v and t a =40 ~ 85 o c. typical values are at t a =25 o c.
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 6 the APW7281 s i2c slave address is a hard-coded 7 bit address 1110101. the APW7281 supports the following write and read protocol and contains 6 registers. i 2 c programming master to slave slave to master s 7bit slave address a 8bit address 8bit data a r/w p 0 7'b1110101 a a= acknowledge (sda low) a= not acknowledge (sda high) s= start condition p= stop condition reg. address reg. data single byte write data transfer format in standard, fast, fast-plus modes master to slave slave to master s 7bit slave address a 8bit address a r/w reg. address 0 sr 7bit slave address 8bit data p reg. data a a r/w 1 a= acknowledge (sda low) a= not acknowledge (sda high) p= stop condition s= start condition sr= repeated start condition single byte read data transfer format in standard, fast, fast-plus modes 7'b1110101 7'b1110101 master to slave slave to master a=acknowledge (sda low) a=not acknowledge (sda high) s=start condition p=stop condition sr=repeated start condition s 8bit master code 0000 1xxx fast speed (400khz) high speed (3.4mhz) a sr 7bit slave address a 8bit address a r/w . reg. address 0 reg. first byte data a p reg. last byte data a 8bit data 8bit data 7'b1110101 sr 7bit slave address 7'b1110101 high speed continues write data transfer format in high speed mode
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 7 register map register address (hex) r/w name power on default description 1 00 read only silicon version register n/a 2 01 r/w configuration register 01h reset, enable, gpio_cfg, ssfm, mode_ctrl 3 02 r/w voutfloorset register 06h adjust voutfloorset from 2.85v to 5.2v 4 03 r/w voutroofset register 0ah adjust voutroofset from 2.85v to 5.2v 5 04 r/w ilimset register 1bh adjust inductor peak current limit 6 05 read only status register n/a tsd/hotdie/dcdcmode/opmode/ilimpt/ilimbst/fault reg00 silicon reversion register data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name silicon_reversion[7:0] read/write r r r r r r r r power on default e-fuse n n n n n n n n bit name bit definition silicon_reversion[7:0] silicon revision bits: 00000000: 1 st version 00000001: 2 nd version 00000010: 3 rd version
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 8 reg01 configuration register data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name reset enable[1:0] reserved gpiocfg ssfm mode_ctrl[1:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w power on default 0 0 0 0 0 0 0 1 e-fuse n y y n y y y y bit name bit definition reset device reset bit: 0: keep current register setting. 1: reset all registers value to default. enable[1:0] device enable bits: 00: device operation follows hardware control signal (refer to table 1). 01: device automatically transits between dc/dc boost and bypass mode regardless of the bypb signal while en=high. 10: device is forced in bypass mode regardless of bypb signal while en=high. 11: device is in shutdown mode; the output voltage is zero regardless of the bypb signal while en=high. reserved reserved. gpiocfg gpio pin configuration bit: 0: gpio pin is configured to support manual reset input (rstb) and interupt generation output (faultb). 1: gpio pin is configured as a device mode selection input., configuring gpio low or high results different mode selection as below: gpio=low: pfm in light load current with automatic transition into pwm operation in heavy load current. gpio=high: device is forced in pwm regardless of light load current conditions. (please also refer to mode_ctrl[1:0] register for more mode selection settings ) ssfm spread modulation control: 0: spread spectrum modulation is disabled. 1: spread spectrum modulation is enabled in dc/dc boost mode. mode_ctrl[1:0] device mode of operation bits: 00: device operation follows hardware control signal (gpio must be configured as mode selection input) 01: pfm with automatic transition into pwm operation. 10: forced pwm operation. 11: pfm with automatic transition into pwm operation (vsel=low), forced pwm operation (vsel=high),
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 9 typical operating characteristics shutdown current vs input voltage input voltage (v) s h u t d o w n c u r r e n t ( u a ) 0 0.5 1 1.5 2 2.5 2 2.5 3 3.5 4 4.5 5 5.5 boost mode shutdown current vs input voltgae input voltage (v) s h u t d o w n c u r r e n t ( u a ) 0 2 4 6 8 10 12 14 16 2 3 4 5 6 2.5 3.5 4.5 5.5 bypass mode v out voltage vs input voltage input voltage (v) v o u t v o l t a g e ( v ) 2 2.5 3 3.5 4 4.5 5 2.5 3 3.5 4 4.5 5 vout=3.35v - :loading=1ma - :loading=100ma - :loading=1000ma - :loading=1500ma v out voltage vs input voltage input voltage (v) v o u t v o l t a g e ( v ) v out =3.15v - :loading=1ma - :loading=100ma - :loading=1000ma - :loading=1500ma 2 2.5 3 3.5 4 4.5 5 2.5 3 3.5 4 4.5 5 loading (a) e f f i c i e n c y ( % ) 80 82 84 86 88 90 92 94 96 98 100 0.0010.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 - :v in =3.6v - :v in =4.3v bypass mode efficiency vs loading e f f i c i e n c y ( % ) efficiency vs loading 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 loading (a) v out =3.35v - :v in =3.3v - :v in =3.0v - :v in =2.7v boost mode
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 10 operating waveforms ch1:v en -5v/div ch2:- ch3:v out -1v/div ch4:i l -500ma/div time:1ms/div power on en - no load ch1 ch4 ch3 boost mode ch1:v en -5v/div ch2:- ch3:v out -1v/div ch4:i l -500ma/div time:2ms/div power off en C no load ch1 ch4 ch3 ch1:v psi -5v/div ch2:- ch3:v out -200mv/div (offset 3.3v) ch4:- time:200us/div vsel low to high to low C loading=50ma ch1 ch3 ch1:v psi -5v/div ch2:- ch3:v out -200mv/div (offset 3.3v) ch4:- time:100us/div vsel low to high to low C loading=500ma ch1 ch3
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 11 operating waveforms (cont.) ch1:v en -5v/div ch2:- ch3:v out -1v/div ch4:i out -500ma/div time:2ms/div power on en C v out shorted to gnd ch1 ch4 ch3 gpio=l
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 12 reg02 voutfloorset register data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name reserved voutfloor_th[5:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w power on default 0 0 0 0 0 1 1 0 e-fuse n n y y y y y y bit name bit definition reserved reserved. output voltge threshold, dc/dc boost / bypass mode change: 000000: 2.850v 001000: 3.250v 010000: 3.650v 011000: 4.050v 100000: 4.450v 101000: 4.850v 000001: 2.900v 001001: 3.300v 010001: 3.700v 011001: 4.100v 100001: 4.500v 101001: 4.900v 000010: 2.950v 001010: 3.350v 010010: 3.750v 011010: 4.150v 100010: 4.550v 101010: 4.950v 000011: 3.000v 001011: 3.400v 010011: 3.800v 011011: 4.200v 100011: 4.600v 101011: 5.000v 000100: 3.050v 001100: 3.450v 010100: 3.850v 011100: 4.250v 100100: 4.650v 101100: 5.050v 000101: 3.100v 001101: 3.500v 010101: 3.900v 011101: 4.300v 100101: 4.700v 101101: 5.100v 000110: 3.150v 001110: 3.550v 010110: 3.950v 011110: 4.350v 100110: 4.750v 101110: 5.150v voutfloor_th[5:0] 000111: 3.200v 001111: 3.600v 010111: 4.000v 011111: 4.400v 100111: 4.800v 101111: 5.200v reg03 voutroofset register data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name reserved voutroof_th[5:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w power on default 0 0 0 0 1 0 1 0 e-fuse n n y y y y y y bit name bit definition reserved reserved. output voltge threshold, dc/dc boost / bypass mode change: 000000: 2.850v 001000: 3.250v 010000: 3.650v 011000: 4.050v 100000: 4.450v 101000: 4.850v 000001: 2.900v 001001: 3.300v 010001: 3.700v 011001: 4.100v 100001: 4.500v 101001: 4.900v 000010: 2.950v 001010: 3.350v 010010: 3.750v 011010: 4.150v 100010: 4.550v 101010: 4.950v 000011: 3.000v 001011: 3.400v 010011: 3.800v 011011: 4.200v 100011: 4.600v 101011: 5.000v 000100: 3.050v 001100: 3.450v 010100: 3.850v 011100: 4.250v 100100: 4.650v 101100: 5.050v 000101: 3.100v 001101: 3.500v 010101: 3.900v 011101: 4.300v 100101: 4.700v 101101: 5.100v 000110: 3.150v 001110: 3.550v 010110: 3.950v 011110: 4.350v 100110: 4.750v 101110: 5.150v voutroof_th[5:0] 000111: 3.200v 001111: 3.600v 010111: 4.000v 011111: 4.400v 100111: 4.800v 101111: 5.200v
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 13 reg04 ilimset register data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name reserved ilim_off soft_star t ilim[3:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w power on default 0 0 0 1 1 0 1 1 e-fuse n n n y y y y y bit name bit definition reserved reserved. ilim_off boost mode high-side mosfet ocp enable/disable control: 0: current limit enabled 1: current limit disabled (ps. high-side mosfet ocp threshold is low-side mosfet ocp threshold + 50%) soft_start soft-start selection bit: 0: dc/dc boost soft-start current is limited per ilim [3:0] bits settings. 1: dc/dc boost soft-start current is limited to ca. 1650ma inductor peak current. ilim[3:0] inductor peak current limit in dc/dc boost mode 0000: 900ma 1000: 1900ma 0001: 950ma 1001: 2400ma 0010: 1000ma 1010: 2900ma 0011: 1050ma 1011: 3400ma 0100: 1150ma 1100: 3900ma 0101: 1250ma 1101: 4400ma 0110: 1450ma 1110: 4900ma 0111: 1550ma 1111: 5400ma
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 14 reg05 status register data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name tsd hotdie dcdcmode opmode ilimpt ilimbst fault reserved read/write r r r r r r r r power on default 0 0 0 0 0 0 0 0 e-fuse n n n n n n n n bit name bit definition tsd thermal shutdown status bit: 0: normal operation 1: thermal shutdown tripped. this flag is reset after readout. hotide instantaneous die temperature bit: 0: t j <115 1: t j >115 dcdcmode dc/dc mode of operation status bit: 0: device operates in pwm mode. 1: device operates in pfm mode. opmode device mode of operation status bit: 0: device operates in by-pass mode. 1: device operates in dc/dc boost mode. ilimpt current limit status bit (by-pass mode): 0: normal operation. 1: indicates that the bypass fet current limit has triggered. this flag is reset after readout. ilimbst current limit status bit (dc/dc boost mode) 0: normal operation. 1: indicates that the average input current limit has been triggered for 1.5ms in dc/dc boost mode, this flag is reset after readout. fault fault status bit: 0: normal operation. 1: indicates that a fault condition has occurred. this flag is reset after readout.
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 15 timing chart v in por_rise 2.3v v en 400us boost mode, normal power on timing chart boost hs pmos enable (linear mode) v out phase 1 timer 750us enable 750us boost converter enable (pwm mode) =v in (by-pass mode) or v out_th (boost mode) por_fall 2.2v 0.65a current limit function enable i l 650ma v in -100mv (or 95%vout_th)
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 16 pin description pin no. name function a3, a4 vin power supply input. b3, b4 vout boost converter output. this is the enable pin of the device. on the rising edge of the enable pin, all the registers are reset with their default values. this input must not be left floating and must be terminated. a1 en en = low: the device is forced into shutdown mode and the i2c control interface is disabled. depending on the logic level applied to the bypb input, the converter can either be forced in pass-through mode or it's output can be regulated to a minimum level so as to limit the input-to-output voltage difference to less than 3.6v (typ). the current consumption is reduced to a few a. en = high: the device is operating normally featuring automatic dc/dc boost, pass-through mode transition. a2 gpio this pin can either be configured as a input (mode selection) or as dual role input/open-drain output (rstb/faultb) pin. per default, the pin is configured as rstb/faultb input/output. the input must not be left floating and must be terminated. b1 vsel vsel signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. this pin must not be left floating and must be terminated. c1 bypb a logic low level on the bypb input forces the device in pass-through mode. this pin must not be left floating and must be terminated. b2 scl serial interface clock line. this pin must not be left floating and must be terminated. c2 sda serial interface address/data line. this pin must not be left floating and must be terminated. c3, c4 sw inductor connection. drain of the internal power mosfet. connect to the switched side of the inductor. d2, d3, d4 pgnd power ground pin. d1 agnd analog ground pin. this is the signal ground reference for the ic.
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 17 block diagram sw bulk select bulk select gate driver e/a v ref pwm control logic i2c interface sda scl en bypb gpio pg mode 300k v en >0.7v 300k v bypb >0.7v vsel 300k v vsel >0.7v pgnd pgnd pgnd agnd control logic vout vin peak current sense ilim[3:0] uvlo otp current sense 1.5*ilim[3:0]
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 18 typical application circuit sw sw vin vin vsel en bypb scl sda pgnd pgnd pgnd agnd gpio vout vout voltage select enable forced bypass/auto i2c bus 1.8v v bat battery 2.5~4.35v 0.47 m h 1.5 m f 10 m f interupt
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 19 package information wlcsp1.6x1.6-16 e e b e 2 pin 1 e d aaa a1 a2 a nx c seating plane 0.008 1.60 1.66 0.063 0.065 s y m b o l min. max. 0.63 0.12 0.20 0.30 1.60 1.66 0.20 a a1 b d e e millimeters a2 0.37 0.43 0.40 bsc wlcsp1.60*1.60-16 0.016 bsc min. max. inches 0.025 0.005 0.015 0.017 0.008 0.012 0.063 0.065 aaa 0.05 0.002
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 20 carrier tape & reel dimensions a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d application a h t1 c d d w e1 f 178.0 2.00 50 min. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 8.0 0.30 1.75 0.10 3.5 0.05 p0 p1 p2 d0 d1 t a0 b0 k0 wlcsp1.6x1.6 4.0 0.10 4.0 0.10 2.0 0.05 1.5+0.10 -0.00 1.5 min. 0.6+0.00 -0.40 1.75 0.15 1.75 0.15 0.75 0.10 (mm) devices per unit package type unit quantity wlcsp(1.6x1.6) tape & reel 3000
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 21 classification profile taping direction information wlcsp1.6x1.6 user direction of feed
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 22 classification reflow profiles profile feature sn-pb eutectic assembly pb-free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) (t s ) 100 c 150 c 60-120 seconds 150 c 200 c 60-120 seconds average ramp-up rate (t smax to t p ) 3 c/second max. 3 c/second max. liquidous temperature (t l ) time at liquidous (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak package body temperature (t p )* see classification temp in table 1 see classification temp in table 2 time (t p )** within 5 c of the specified classification temperature (t c ) 20** seconds 30** seconds average ramp-down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb-free process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm C 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 220 c 3 2.5 mm 220 c 220 c test item method description solderability jesd-22, b102 5 sec, 245 c holt jesd-22, a108 1000 hrs, bias @ tj=125 c pct jesd-22, a102 168 hrs, 100 % rh, 2atm, 121 c tct jesd-22, a104 500 cycles, -65 c~150 c hbm mil-std-883-3015.7 vhbm R 2kv mm jesd-22, a115 vmm R 200v latch-up jesd 78 10ms, 1 tr R 100ma reliability test program
copyright ? anpec electronics corp. rev. a.1 - mar., 2017 APW7281 www.anpec.com.tw 23 customer service anpec electronics corp. head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 2f, no. 11, lane 218, sec 2 jhongsing rd., sindian city, taipei county 23146, taiwan tel : 886-2-2910-3838 fax : 886-2-2917-3838

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